Semiconductor device and fabrication method therefor

ABSTRACT

A method of efficiently and inexpensively fabricating a chip-size package having an electrode pitch expanded by forming a conductor wiring on the electrode forming surface side of a semiconductor chip, especially, a method for facilitating wiring and bump forming. A semiconductor device comprising a semi-conductor elements and conductor wirings formed on the semiconductor elements by etching wiring-forming metal foil; and a fabrication method for a semiconductor device comprising the steps of laminating wiring forming metal foil on the electrode forming surface side on the semiconductor, forming a resist wiring pattern on the metal foil, etching the metal foil, and slicing the device into individual elements.

TECHNICAL FIELD

This invention concerns a chip-size semiconductor device formed withconductor wirings for re-arranging electrodes on an IC chip and it,particularly, relates to a fabrication method capable of collectiveprocessing at the wafers.

BACKGROUND ART

In recent years, size-reduction, enhancement for function, higherintegration degree and multiple pin arrangement have been progressedremarkably for IC package. Further, CSP as a package of a size identicalwith a chip-size has been developed recently.

JP-A-11-121507 proposes a method of packaging in a state of wafer andfabricating a chip-size package. However, in this method, bumps forconnecting an IC package with the outside are formed at electrodepositions in IC. In recent tend for the reduction of chip-size andmultiple pin arrangement, the pitch for arranging electrodes of the chiphas been narrowed more and more and it is necessary to re-arrange theelectrodes on the IC chip to expand the electrode pitch for facilitatingsubsequent mounting.

This invention intends to solve the foregoing problems in the prior artand provide a method of fabricating a chip-size package in which theelectrode pitch is extended by forming conductor wirings on the side ofthe electrode forming surface of a semiconductor element efficiently andat a reduced cost and, particularly, to provide a method capable offorming wirings and bumps easily.

DISCLOSURE OF THE INVENTION

The present inventors have found that the foregoing object can be solvedby laminating a wiring-forming metal foil on the side of formingelectrodes of a semiconductor wafer formed at the surface thereof withcircuit elements by using a bonding technique between a metal foil andceramics previously filed by the present inventors (refer toInternational Publication No. WO99/58470), and then etching the metalfoil to form wirings and dividing the same into individual elements.

Further, it has been found for the formation of bumps that bumps can beformed by laminating a wiring-forming multi-layered metal foil to asemiconductor wafer formed at the surface thereof with circuit elementson the side of the electrode forming surface and by merely etching thewirings having bumps thereon.

That is, this invention described in claim 1 provides a semiconductordevice comprising a semiconductor element and conductor wirings on thesemiconductor element formed by etching a wiring-forming metal foil(hereinafter referred to as a first embodiment of this invention).

In this case, it is preferred that the wiring-forming metal foil iscopper.

Further in this case, the thickness of the wiring-forming metal foil ispreferably 1 to 100 μm.

The semiconductor device of the first embodiment according to thisinvention described above is obtained by a step of laminating awiring-forming metal foil to a semiconductor wafer formed at the surfacethereof with circuit elements on the electrode forming surface side, astep of forming a resist wiring pattern on the metal foil, a step ofetching the metal foil and a step of dividing into individual elements.

In this case, it is preferred that the wiring-forming metal foil iscopper.

Further in this case, it is preferred that the thickness of thewiring-forming metal foil is 1 to 100 μm.

Further in this case, it is preferred that the semiconductor waferformed at the surface thereof with circuit elements is a semiconductorwafer formed at the surface thereof with a metal thin film.

Further, another embodiment of the invention provides a semiconductordevice comprising a semiconductor element, conductor wirings formed onthe semiconductor element formed by etching a wiring-forming metal foiland solder bumps (hereinafter referred to as a second embodiment of thisinvention).

In this case, it is preferred that the wiring-forming metal foil iscopper.

Further in this case, it is preferred that the thickness of thewiring-forming metal foil is 1 to 100 μm.

The semiconductor device according to the second embodiment of thisinvention is obtained by a step of laminating a wiring-forming metalfoil to the semiconductor wafer formed at the surface thereof withcircuit elements on the electrode forming surface side, a step offorming a resist wiring pattern on the metal foil, a step of etching themetal foil, a step of forming solder bumps and a step of dividing intoindividual elements.

In this case, it is preferred that the wiring-forming metal foil iscopper.

Further in this case, it is preferred the thickness of thewiring-forming metal foil is 1 to 100 μm.

Further, in this case, it is preferred that the semiconductor waferformed at the surface thereof with circuit elements is a semiconductorwafer formed at the surface thereof with a metal thin film.

Further, another embodiment of the invention provides a semiconductordevice comprising a semiconductor element and a conductor wiring havingbumps on the semiconductor element (hereinafter referred to as a thirdembodiment of this invention).

In this case, it is desirable that the wiring-forming multi-layeredmetal foil is a metal laminate comprising three layers of bump-formingcopper or solder foil/etching stopper layer nickel/wiring-forming copperfoil and, further, it is preferred the thickness of the bump formingcopper or solder foil is from 10 to 100 μm. Further, the etching stopperlayer nickel is preferably nickel plating of 0.5 to 3 μm thickness ornickel foil clad of 1 to 10 μm thickness.

Further, in this case, it is preferred that the thickness of thewiring-forming copper foil is 1 to 100 μm.

The semiconductor device of the third embodiment according to thisinvention as described above can be fabricated by a method offabricating a semiconductor device including a step of laminating awiring-forming multi-layer metal foil to a semiconductor wafer formed atthe surface thereof with circuit elements on the electrode formingsurface side, a step of forming a bump-forming resist wiring pattern onthe multi-layered metal foil, a step of selectively etching the metalfoil, a step of removing the etching stopper layer, a step of forming awiring-forming resist wiring pattern and a step of forming wirings byetching, and a step of dividing into individual elements.

In the fabrication method of the semiconductor device, it is preferredthat the wiring-forming multi-layered metal foil is a metal laminatecomprising three layers of a bump forming copper or solder foil/etchingstopper layer nickel/wiring forming copper foil. Further, it ispreferred that the thickness of the bump-forming copper or solderingfoil is 10 to 100 μm. Further, the etching stopper layer nickel ispreferably nickel plating of 0.5 to 3 μm thickness or nickel foil cladof 1 to 10 μm thickness. Further, it is preferred that the thickness ofthe wiring-forming copper foil is 1 to 100 μm.

Further, in the method of fabricating the semiconductor device, thesemiconductor wafer formed at the surface thereof with circuit elementsis preferably a semiconductor wafer formed at the surface thereof with athin metal film.

The semiconductor device according to this invention comprises asemiconductor element, a conductor wiring having bumps on thesemiconductor element formed by etching a wiring-forming multi-layeredmetal foil, an insulative resin and solder bumps.

The method of fabricating the semiconductor device according to thisinvention includes a step of laminating a wiring-forming multi-layeredmetal foil to the semiconductor wafer formed at the surface thereof withcircuit elements on the electrode forming surface side, a step offorming a bump-forming resist wiring pattern on the multi-layered metalfoil, a step of selectively etching the metal foil, a step of removingthe etching stopper layer, a step of forming wiring-forming resistwiring pattern, and a step of forming wirings by etching, a step ofcoating an insulative resin and polishing the surface thereof, a step offorming solder bumps and a step of dividing into individual elements.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a view showing an example of a circuit forming step for afirst embodiment and a second embodiment according to this invention(step of laminating a wiring copper foil on a semiconductor wafer).

FIG. 2 is a view showing an example of a circuit forming step in a firstembodiment and a second embodiment according to this invention (step offorming conductor wirings on the wiring copper foil).

FIG. 3 is a view showing an example of a circuit forming step in thefirst embodiment according to this invention (step of cutting intoindividual elements).

FIG. 4 is a view showing an example of a circuit forming step in thefirst embodiment according to this invention (element after cutting).

FIG. 5 is a view showing an example of a circuit forming step in thesecond embodiment according to this invention (step of forming solderbumps on wiring copper foil).

FIG. 6 is a view showing an example of a circuit forming step in thesecond embodiment according to this invention (step of cutting intoindividual elements).

FIG. 7 is a view showing an example of a circuit forming step in thesecond embodiment according to this invention (element after cutting).

FIG. 8 is a view showing an example of a circuit forming step in a thirdembodiment according to this invention (step of laminating a wiringcopper foil on a semiconductor wafer).

FIG. 9 is a view showing an example of a circuit forming step in thethird embodiment according to this invention (forming bumps).

FIG. 10 is a view showing an example of a circuit forming step in thethird embodiment according to this invention (selective etching ofetching stopper layer nickel).

FIG. 11 is a view showing an example of a circuit forming step in thethird embodiment according to this invention (selective etching ofwiring-forming copper foil).

FIG. 12 is a view showing an example of a circuit forming step in thethird embodiment according to this invention (step of cutting intoindividual elements).

FIG. 13 is a view showing an example of a circuit forming step in thethird embodiment according to this invention (element after cutting).

FIG. 14 is a view showing a step of coating an insulative resin andsurface polishing in a fourth embodiment according to this invention.

FIG. 15 is a view showing a step of forming solder bumps in the fourthembodiment according to this invention.

FIG. 16 is a view showing a step of cutting into individual elements inthe fourth embodiment according to this invention.

FIG. 17 is a view showing an element after cutting in the fourthembodiment according to this invention.

FIG. 18 is a front elevational view of an element after cutting in thefirst, second, third or fourth embodiment according to this invention.

BEST MODE FOR PRACTICING THE INVENTION

At first, a first embodiment according to this invention is to bedescribed.

The first embodiment according to this invention concerns asemiconductor device comprising a semiconductor wafer formed at thesurface thereof with circuit elements, and conductor wirings on thesemiconductor element formed by etching a wiring-forming metal foil.

As the semiconductor, a semiconductor wafer or the like used ordinarilycan be used and, as the wiring-forming metal foil, a foil preferablyformed of copper with a thickness of 1 to 100 μm can be used. Theconductor wirings can be formed appropriately into a desired shape.

The semiconductor device in the first embodiment according to thisinvention can be fabricated by a method of fabricating a semiconductordevice including a step of laminating a wiring-forming metal foil to asemiconductor wafer formed at the surface thereof with circuit elementson the electrode-forming surface side, a step of forming a resist wiringpattern on the metal foil, a step of etching the metal foil and a stepof dividing into individual elements.

As the substrate, those used ordinarily such as a semiconductor waferformed at the surface thereof with circuit elements can be used. As thewiring-forming metal foil, a foil preferably formed of copper and of 1to 100 μm thickness can be used as described above.

Depending on the case, a thin metal film can be provided on thesemiconductor wafer formed at the surface thereof with circuit elementsby using a sputtering method, a vapor deposition method or the likeafter surface cleaning. This can facilitate lamination of the metal foilon the semiconductor wafer. As the metal forming the thin film, Cr, Mo,W or the like is used as a barrier metal in a case where the chipelectrode of the semiconductor is Al, but the subsequent removal byetching is difficult. Then, with a view point for the ease of etchingelimination, use of nickel is preferred.

Lamination of the wiring-forming metal foil to the semiconductor wafercan be conducted by using the technique described in InternationalPublication No. WO99/58470 previously filed by the present inventors(FIG. 1).

After lamination, a resist is coated on the wiring forming metal foiland then exposure and development are conducted to form a resist wiringpattern. The resist wiring pattern is formed preferably such that it canbe easily divided subsequently into individual elements and it canadopt, for example, a method of not coating the resist to portions forthe division.

A series of procedures such as resist coating, exposure and developmentcan be conducted based on the ordinary method.

Then, the wiring-forming metal foil is etched. In a case where the metalfoil is copper, a commercially available alkali type copper etchingsolution can be used as the etching solution.

Successively, the resist is removed to form wirings (FIG. 2).

Finally, it is divided into individual elements that is, as describedabove, in a case where the portions for the division formed upon resistwiring pattern formation for indicating the boundary between each ofindividual element regions are made distinct, it is divided intoindividual elements with reference to the portions (FIGS. 3, 4).

Division is conducted by using a diamond blade, laser or the like.

At first, a second embodiment of this invention is to be described.

The second embodiment of this invention concerns a semiconductor devicecomprising a semiconductor element, conductor wirings on thesemiconductor element formed by etching a wire-forming metal foil andsolder bumps.

The semiconductor, the wiring-forming metal foil and the conductorwirings are identical with those described for the first embodiment ofthis invention.

The semiconductor device described above can be fabricated by a methodof fabricating a semiconductor device including a step of laminating awiring-forming metal foil to a semiconductor wafer formed at the surfacethereof with circuit elements on the electrode forming surface side, astep of forming a resist wiring pattern on the metal foil, a step ofetching the metal foil, a step of forming solder bumps and a step ofdividing into individual elements.

As the substrate, a semiconductor wafer formed at the surface thereofwith circuit elements can be used usually and, depending on the case, athin metal film can be provided after surface cleaning of thesemiconductor wafer or the like. Further, lamination of thewiring-forming metal foil to the semiconductor wafer can be conducted inthe same manner as in the first embodiment of this invention, by usingthe technique described in International Publication No. WO99/58470previously filed by the present inventors (FIG. 1).

After the lamination, like the first embodiment of this invention, aresist is coated on the wiring-forming metal foil and then exposure anddevelopment are conducted to form a resist wiring pattern and,successively, the wiring-forming metal foil is etched and then theresist is removed to form wirings (FIG. 2). The resist wiring pattern ispreferably applied so as to be divided easily into individual elementssubsequently like the first embodiment.

In the second embodiment of this invention, solder bumps aresuccessively formed (FIG. 5). The solder bumps are formed at thepositions for re-arranging electrodes.

Finally, it is divided into individual elements (FIGS. 6, 7). Divisionis identical with that in the first embodiment of this invention.

Successively, a third embodiment according to this invention is to beexplained.

The third embodiment of this invention concerns a semiconductor devicecomprising a semiconductor element, and conductor wirings having bumpson the semiconductor element formed by etching the wiring-formingmulti-layered metal foil.

The semiconductor device, the wiring-forming metal foil and theconductor wirings are identical with those described for the firstembodiment and the second embodiment of this invention.

The thickness of the conductor wirings is 1 to 100 μm as describedabove, and for the etching stopper layer, nickel plating of 0.5 to 3 μmthickness, preferably, 1 to 2 μm thickness or nickel foil clad of 1 to10 μm thickness, preferably, 2 to 5 μm thickness can be used.

The thickness of the bump is 10 to 100 μm, preferably, 10 to 50 μm.

The semiconductor device according to the third embodiment of thisinvention described above can be fabricated by a method of fabricating asemiconductor device including a step of laminating a wiring-formingmulti-layered metal foil to a semiconductor formed at the surfacethereof with circuit elements on the electrode forming surface side, astep of forming a bump-forming resist wiring pattern on themulti-layered metal foil, a step of selectively etching the metal foil,a step of removing the etching stopper layer, a step of forming awiring-forming resist wiring pattern and a step of forming wirings byetching, and a step of dividing into individual elements.

At first, a wiring-forming metal laminate is laminated to thesemiconductor wafer formed at the surface thereof with circuit elementson the electrode forming surface side (FIG. 8). For the wiring-formingmetal laminate, a metal laminate comprising, for example, a bump-formingcopper or solder foil (10 to 100 μm thickness)/etching stopper layernickel (0.5 to 3 μm thickness in a case of plating and 1 to 10 μmthickness in a case of foil)/wiring copper foil (1 to 100 μm).

Lamination can be conducted in the same manner as described for theportion of the first embodiment and the second embodiment of thisinvention.

After the lamination, resist is coated on the metal laminate and thenexposure and development are conducted to form a bump-forming resistpattern.

Then, the bump forming layer in the metal laminate is selectively etched(FIG. 9). In a case where the bump-forming layer is a copper foil,etching is conducted by using a selective copper etching solution such acommercially available alkali type copper etching solution to formbumps.

Successively, the etching stopper layer is removed.

In a case where the etching stopper layer is nickel plating or foil, acommercially available nickel removing solution (for example, N-950,manufactured by Mertex Co.) can be used (FIG. 10).

Further, a wiring-forming resist wiring pattern is formed. In this case,the resist wiring pattern is preferably applied so as to indicate theboundary between each of element regions corresponding to the divisioninto individual element regions to be described later, which isidentical with that for the first embodiment and the second embodimentof this invention.

Successively, the wiring layer is etched. In a case where the wiringlayer is copper, a commercially available alkali type copper etchingsolution or the like can be used. After forming wirings by etching, theresist is removed (FIG. 11).

Finally, it is divided into individual elements (FIGS. 12, 13). Divisioncan be conducted by the same means as in the first and the secondembodiments of this invention.

EXAMPLE Example 1 First Embodiment of this Invention

-   (1) Material

A semiconductor wafer 1 formed at the surface thereof with circuitelements and a wiring-forming copper foil (15 μm thickness) 2 laminatedby the method disclosed in International Publication WO99/58470 wereused as a substrate (FIG. 1).

Before lamination, a thin metal film (nickel) was provided on thesemiconductor wafer by using, for example, a sputtering method or avapor deposition method.

-   (2) Formation of wirings

After coating a resist on the copper foil, exposure and development wereconducted to form a resist wiring pattern. Then, copper was etched toform wirings 3 (FIG. 2).

-   (3) It was divided into individual elements (FIGS. 3, 4, 18).

Example 2 Second Embodiment of this Invention

-   (1) Material

A semiconductor wafer 1 formed at the surface thereof with circuitelements and a wiring-forming copper foil (15 μm thickness) 2 laminatedin the same manner as in Example 1 were used as a substrate (FIG. 1).

-   (2) Formation of wirings

After coating a resist on the copper foil, exposure and development wereconducted to form a wiring-forming resist wiring pattern. Then, copperwas etched to form wirings 3 (FIG. 2).

-   (3) Formation of solder bumps

Solder bumps 4 were formed on wirings at the positions for re-arrangingelectrodes (FIG. 5).

-   (4) It was divided into individual elements (FIGS. 6, 7, 18)

Example 3 Third Embodiment of this Invention

-   (1) Material

A metal laminate comprising bump forming copper foil (35 μm thickness)5/etching stopper layer nickel (plating thickness of 1 μm)6/wiring-forming copper foil (15 μm) 1 was laminated to a semiconductorwafer formed at the surface thereof with circuit elements (identicalwith that used in Example 1 (FIG. 8).

-   (2) Pattern formation

After coating a resist on the metal laminate, exposure and developmentwere conducted to form a bump-forming resist wiring pattern.

-   (3) Etching

Copper was selectively etched by using a commercially available copperetching solution such as an alkali type copper etching solution to formbumps 7 (FIG. 9).

-   (4) Removal of etching stopper layer

The etching stopper layer nickel 6 was removed by using a commerciallyavailable nickel removing solution (N-950, manufactured by Mertex Co.)(FIG. 10)

-   (5) A wiring-forming resist wiring pattern was formed.-   (6) Etching was conducted by using a copper etching solution such as    an alkali type copper etching solution to form wirings 3 and then    the resist was removed (FIG. 11).-   (7) It was divided into individual elements (FIGS. 12, 13, 18).

Example 4 Fourth Embodiment of this Invention

-   (1) Material

A metal laminate comprising bump forming copper foil (35 μm thickness)5/etching stopper layer nickel (plating thickness 1 μm) 6/wiring-formingcopper foil (15 μm) 1 was laminated to a semiconductor wafer formed atthe surface thereof with circuit elements (identical with that used inExample 1 (FIG. 8).

-   (2) Pattern formation

After coating a resist on the metal laminate, exposure and developmentwere conducted to form a bump-forming resist wiring pattern.

-   (3) Etching

Copper was selectively etched by using a commercially available copperetching solution such as an alkali type copper etching solution to formbumps 7 (FIG. 9).

-   (4) Removal of etching stopper layer

The etching stopper layer nickel 6 was removed by using a commerciallyavailable nickel removing solution (N-950, manufactured by Mertex Co.)(FIG. 10)

-   (5) A wiring-forming resist wiring pattern was formed.-   (6) Etching was conducted by using a copper etching solution such as    an alkali type copper etching solution to form wirings 3 and then    the resist was removed (FIG. 11).-   (7) An insulative resin such as a polyimide is coated entirely on    the semiconductor wafer to apply resin encapsulation. Subsequently,    polishing is conducted so as to expose copper bumps to the surface    (FIG. 14).-   (8) Solder bumps are formed by using a printing method or the like    (FIG. 15)-   (9) It was divided into individual elements (FIGS. 16, 17, 18).

INDUSTRIAL APPLICABILITY

According to this invention, a chip-size package in which an electrodepitch is expanded by forming conductor wirings to a semiconductor on theelectrode forming surface side can be fabricated efficiently and at areduced cost. Particularly, wirings and bumps can be formed easily.

Accordingly, the semiconductor device and the wiring forming methodaccording to this invention are useful in the field of semiconductors.

The invention claimed is:
 1. A method of fabricating a semiconductordevice including a step of laminating a wiring-forming multi-layeredmetal foil consisting of three layer of metal foil/etching stopperfoil/metal foil to a semiconductor wafer formed at the surface thereofwith circuit elements on the electrode forming surface side, a step offorming a bump-forming resist wiring pattern on the multi-layered metalfoil, a step of selectively etching the metal foil, a step of removingthe etching stopper layer, a step of forming a wiring-forming resistwiring pattern and a step of forming wirings by etching, a step ofcoating an insulative resin onto the wafer and polishing the surface ofthe insulative resin, a step of forming solder bumps, and a step ofdividing into individual elements.